Amplifiers are typically used to amplify low-level audio signals in order to drive audio speakers such as headphones, loudspeakers, and/or other audio devices. Class-D amplifiers have a relatively high efficiency and are particularly applicable to portable audio devices. However, Class-D amplifiers are also used in non-portable audio applications. Class-D amplifiers include power transistors that are operated in either a fully-on or a fully-off state. A Class-D amplifier generates an amplified binary signal that conveys the same information as a digital input signal.
Referring to FIGS. 1 and 2, an exemplary Class-D amplifier 10 includes a digital signal processor (DSP) 12 that receives a digital audio input signal. Alternatively, the Class-D amplifier 10 may include an application-specific integrated circuit (ASIC) or another integrated circuit instead of or in addition to the DSP 12. The DSP 12 amplifies the input signal and generates a pulse width modulated (PWM) signal based on the input signal. In an exemplary embodiment, the amplifier 10 is a tri-state amplifier 10, and the PWM signal consists of three values. For example, the values may be −1, 0, and +1.
A sourcing transistor 14, a sinking transistor 16, and a ground transistor 18 all receive the PWM signal. The sourcing transistor 14 communicates with a positive supply potential Vdd, the sinking transistor 16, and the ground transistor 18. The sinking transistor 16 communicates with a negative supply potential −Vdd, the sourcing transistor 14, and the ground transistor 18. The ground transistor 18 communicates with a ground potential, the sourcing transistor 14, and the sinking transistor 16.
The PWM waveform functions as a digital control signal that switches the sourcing and sinking transistors 14 and 16, respectively, on and off based on the amplitude of the input signal. The gain of the amplifier 10 is adjusted by varying the value of the positive and negative supply potentials. The sourcing and sinking transistors 14 and 16, respectively, generate a high-power version of the PWM waveform, which includes components of the input signal as well as components resulting from the PWM conversion process. Therefore, a low-pass filter 20 receives the amplified PWM waveform and outputs lower frequency signals while restricting higher frequency signals. The low-pass filter 20 also has the effect of smoothing transitions in the amplified PWM waveform.
The filtered waveform is received by a load 22 that communicates with a ground potential. For example, the load 22 may be an audio speaker. The ground transistor 18 is turned on in order to ground the common node between the sourcing and sinking transistors 14 and 16, respectively, the ground transistor 18, and the low-pass filter 20. In the event that the low-pass filter 20 includes one or more inductors, the ground transistor 18 provides a ground path to discharge the inductors. This prevents adverse effects to the amplifier circuit 10 that may be caused by the inductors remaining in a charged state.
The DSP 12 includes a sawtooth generator 28 that generates a sawtooth reference signal 30. As shown in FIG. 2, the DSP utilizes the sawtooth reference signal 30 to sample a digital audio input signal 32. A frequency of the sawtooth waveform 30 determines a sampling rate for the input signal 32. The DSP 12 detects intersection points of the input signal 32 and the ramp portions of the sawtooth waveform 30. The intersection points are converted into a PWM waveform 34. The PWM waveform 34 includes positive pulses 36 and negative pulses 38. The amplitudes of the pulses 36 and 38 are equal to the supply potential of the amplifier 10.
Intersection points that are located below zero are converted into negative pulses 38 in the PWM waveform 34. Intersection points that are located above zero are converted into positive pulses 34. Positive pulses 36 begin at reference times of the sawtooth waveform 30. For example, the reference times may occur at points where the ramp portions of the sawtooth waveform 30 are equal to zero. Positive pulses 36 end at respective intersection points of the input signal 32 and the sawtooth waveform 30. Negative pulses 38 begin at intersection points that are located below zero and end at respective reference times of the sawtooth waveform 30. This results in the PWM waveform 34, which exhibits one of three states.
There is a delay time at the DSP 12 associated with processing the input signal 32 and generating the PWM waveform 36. Therefore, the DSP 12 is typically required to temporarily store incoming and/or outgoing data in order to avoid unintentionally discarding data. In one approach, a data buffer is used to temporarily store incoming and/or outgoing data to/from the DSP 12. However, it is necessary but difficult to synchronize a first rate at which a data buffer receives data and a second rate at which the data buffer outputs data in order to avoid buffer underflow and/or overflow conditions. Additionally, this difficulty is compounded when data buffers are included at both the input and the output of the DSP 12. In this case, data rate synchronization is required with respect to each of the data buffers individually and with respect to both of the data buffers collectively. This is necessary to ensure that data is received and output by the DSP 12 consistently and at the same rate.